Traditionally, fast write and erase speeds associated with embedded NVM technologies rely on processes utilizing a high number of masks and complex integrations with high-voltage MOSFETs (metal-oxide-semiconductor field-effect transistors) devices such as LDMOS (laterally diffused metal oxide semiconductor) devices. Although device manufacturers have produced embedded NVM devices using fewer masks and simpler integration processes, each of these NVM devices suffers from at least one of relatively large cell size, low bit density, slow write speeds, and no erase functions (e.g., one-time programming (OTP) only). In addition, such NVM devices may require LDMOS devices along with the standard logic CMOS (complementary MOS) flow. As an example, FIG. 1 illustrates memory cell 101 that includes only one bitline (e.g., NMOS bitline 103) along with its other components, such as control gate structures 105, floating gate structure 107, wordline gate structure 109, select gate structure 111, control gate line 113, NMOS select line 115, and PMOS select line 117. Consequently, devices based on memory cell 101 may exhibit low bit density and large device size, among other disadvantages.
A need therefore exists for more efficient and effective NVM cells that are smaller in size, enable fast write and erase operations, have high bit density, and do not require LDMOS devices, and enabling methodology.